AND‐inverse detecting circuit for the combinatorial logic circuits
Shigeya Tsuiki, Takahiro Haga · Electronics and Communications in Japan (Part III Fundamental Electronic Science) · 1990
Abstract This paper studies an error‐detecting hardware scheme for combinatorial logic circuits (herein called the coincidence scheme). Compared with the softward scheme, the hardware scheme has several merits such as: (1) simultaneous detection of the errors when they occur doing usual operations; and (2) the possibility of detecting the intermittent faults, etc. However, the detecting circuit must be sufficiently smaller than the logic circuit, because if the errors in the detecting circuit cannot be neglected, the detecting signal may be meaningless. For such a small detecting circuit, an AND‐Inverse detecting circuit is proposed which is a special case of the coincidence scheme and also a variation of the conventional Inverse scheme. The AND‐Inverse detecting circuit can be constructed only by 2 AND and 1 EXOR elements except NOT elements. Also, it can detect any stuck‐at faults at the input and/or output points. To clarify such features, we compare it with the Inverse detecting circuit from three measures such as: (1) detecting ability, (2) detecting rate, and (3) redundancy.