Testable design for cell‐based design ASICs and its application to VLSI image signal processor
Hiroyuki Kawai, Shin‐Ichi Nakagawa, Masahiko Yoshimoto, Yasutaka Horiba, Takuji Ogihara, Akiharu Tada · Electronics and Communications in Japan (Part III Fundamental Electronic Science) · 1993
Abstract This paper proposes a testing method which provides an efficient test for the library macrocell built in a large‐scale and high‐speed application‐specific IC (ASIC) of a cell‐based design, especially in the parallel processor for the image processing VLSI. The proposed method consists of the test pattern assembly tool and the testability design for the efficient test. The test pattern is assembled automatically from the test pattern library of the macrocell and the access sequence description, which describes the access procedure from the external pins of the LSI and/or scan registers to the input/output pins of the macrocell built in the LSI. By the foregoing description, the access to the macrocell through the sequential circuit also is possible. With regard to the design for testability, the clock control method, the bus driver circuit, and the test mode control method are newly devised and are combined with the system bus and the scan register. The proposed method is applied to the high‐speed image processing VLSI. The test patterns for four library macrocells in the LSI (two RAMs, multiplier, and PLA) were assembled in one day. The proposed method can also be applied to the user developed macrocell which is utilized iteratively in an LSI. The increase of the number of transistors and the transistor area is suppressed to 3.1 percent (in regard to logic unit) and 0.6 percent (in regard to the whole chip area), respectively. It is verified that there is little decrease of the operational speed in the system operation and does not affect the high‐speed image processing.