Improved Approximations of Crossings in Graph Drawings and VLSI Layout Areas
Guy Even, Sudipto Guha, Baruch Schieber · SIAM Journal on Computing · 2002
We give improved approximations for two classical embedding problems: (i) minimizing the number of crossings in a drawing on the plane of a bounded degree graph; and (ii) minimizing the VLSI layout area of a graph of maximum degree four. These improved algorithms can be applied to improve a variety of VLSI layout problems. Our results are as follows. (i) We compute a drawing on the plane of a bounded degree graph in which the sum of the numbers of vertices and crossings is O(log 3 n )$ times the optimal minimum sum. This is a logarithmic factor improvement relative to the best known result. (ii) We compute a VLSI layout of a graph of maximum degree four in a square grid whose area is O(log 4 n )$ times the minimum layout area. This is an O(log 2 n ) improvement over the best known long-standing result.