High speed architectures for approximate fixed-point division and square root realization
Peng Keong. Lim, M.A. Sid-Ahmed, GRAHAM A. JULLIEN · International Journal of Electronics · 1989
High speed architectures for fixed-point division and square root calculations are developed based on an approximate fast log and antilog algorithm. The architectures can be utilized in applications where high speed is required, and a low percentage error can be tolerated. Error analysis and an application example where the divider architecture is utilized are also presented.