Shared At-Speed BIST for Parallel Test of SRAMs with Different Address Sizes
Tomonori Sasaki, Yoshiyuki Nakamura, Toshiharu Asaka · 2008
Since the area ratio of SRAM occupied in SoC is over 60%, SRAMs usually share a BIST circuit. However, conventional shared BIST cannot perform at-speed test on a part of SRAM when it is shared by different address size SRAMs. We show a solution to this problem with slight extra area overhead and test time.