High defect coverage with low-power test sequences in a BIST environment
Patrick Girard, C. Landrault, S. Pravossoudovitch, A. Virazel, Hans-Joachim Wunderlich · IEEE Design & Test of Computers · 2002
A new technique, random single-input change (RSIC) test generation, generates low-power test patterns that provide a high level of defect coverage during low-power BIST of digital circuits. The authors propose a parallel BIST implementation of the RSIC generator and analyze its area-overhead impact.