Digit-serial AB2 systolic architecture in GF(2m)
N.-Y. Kim, K.-Y. Yoo · IEE Proceedings - Circuits Devices and Systems · 2005
The paper presents a digit-serial-in-serial-out systolic architecture for performing an AB2 operation in GF(2m). If the appropriate digit size is selected, the proposed method can meet the throughput requirement of a specific application with minimum hardware. In addition, the area-time complexity of the pipelined digit-serial AB2 systolic architecture is approximately 10.9% lower than that of the nonpipelined version when m=160 and L=8.