Verification of asynchronous circuits based on zero-suppressed BDDs
Koichi Masukura, Minoru Tomisaka, Tomohiro Yoneda · Systems and Computers in Japan · 2001
Since asynchronous circuits do not use clocks and perform operations based on causality relation between signal transitions, it is regarded that higher speed implementation and lower power consumption implementation than synchronous circuits are possible. In the design verification, however, since the number of states increases essentially more than in synchronous circuits, the computational time required in the verification increases. Accordingly, this paper proposes realization of verification based on trace theory by using ZBDD operations. Moreover, we will show that the higher speed implementation is possible by using Petri nets with inhibitor arcs, reducing the ZBDD variables by performing the composition of modules beforehand, and using special ZBDD operations for Petri nets. Finally, we will package the proposed scheme and carry out verification of several asynchronous circuits. © 2001 Scripta Technica, Syst Comp Jpn, 32(2): 43–54, 2001