A Modular Ring Architecture for Large Scale Neural Network Implementations
L.B. Jump, Panos A. Ligomenides · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 1989
Constructing fully parallel, large scale, neural networks is complicated by the problems of providing for massive interconnectivity and of overcoming fan in/out limitations in area-efficient VLSI/WSI realizations. A modular, bus switched, neural ring architecture employing primitive ring (pRing) processors is proposed, which solves the fan in/out and connectivity problems by a dynamically reconfigurable communication ring that synchronously serves identical, radially connected, processing elements. It also allows cost versus performance trade-offs by the assignment of variable numbers of logical neurons to each physical processing element.