ADAPTIVE SCHEDULED EXPERIMENTATION AND FAULT LOCATION IN LARGE COMBINATIONAL LOGIC NETWORKS
SUNIL RANJAN DAS · Cybernetics & Systems · 1988
For a large combinational circuit, the problem of multiple fault detection and location is of great importance in the sense that, by such detection and location, we may find some fault-free sensitized paths between the primary inputs and some embedded points so that the signal values on these embedded points can be controlled through those paths. Furthermore, for VLSI chips, if some multiple faults frequently occur in certain chip area, fault location may provide some useful insight for redesigning that part of the chip so as to eliminate those multiple faults. In the present paper we develop an approach to multiple fault location which is adaptive scheduled and applicable to large combinational circuits. It is well known that unlike fault detection, adaptive scheduled fault location, in general, yields a shorter experiment. The relative advantages of the suggested approach in the context of some of the existing approaches to the solution of the problem are also discussed.