A pipelined low power architectural MPEG-4 video codec chip with deblocking filter for mobile wireless multimedia applications
Bontae Koo, Seongmin Kim, Seokho Lee, Minseok Choi, Ki-Hyuk Park, Nak-Woong Eum, Jong-Dae Kim, Hyun-Mook Cho · 2003
We present a low-power MPEG-4 video codec chip capable of delivering high-quality video data in mobile wireless multimedia applications. The discussions focus on the architectural design techniques for implementing a high-performance and low power consumption video compression/decompression chip. By introducing partitioning of HW/SW modules, the efficiently optimized frame memory interface architecture, motion estimation skip scheme, and macroblock based pipeline deblocking filtering scheme, the proposed MPEG-4 video codec has low power consumption for mobile wireless multimedia application such as mobile phone, PDA and DMB. The proposed MPEG-4 video codec can perform 30 frames/s of QCIF or 7.5 frame/s of CIF at 27MHz with 128k-144kbps rates. Power consumption is 290mW and the chip size is 9.7mm t 9.7mm at 0.35 mm CMOS technology.