The instruction decoding unit for the VLSI 432 general data processor
Jon A. Bayliss, Stephen R. Colley, R. Kravitz, G.A. McCormick, W.S. Richardson, Doran K. Wilde, L.L. Wittmer · IEEE Journal of Solid-State Circuits · 1981
The instruction decoding unit (IDU), which is one of the two components used to implement a 32-bit VLSI, object-oriented general data processor is described. The instruction decoder is particularly novel in its ability to decode variable length, bit-aligned instructions at high speed. A brief discussion is given on both the organization of the variable length instructions and the microarchitecture of the general data processor. Some of the extensions made to classic state machine concepts are presented, along with a discussion of the circuits used to implement these extensions. Finally, the timing requirements and their associated circuit constraints are discussed.