On fault equivalence, fault dominance, and incompletely specified test sets
Irith Pomeranz, Sudhakar M. Reddy · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2005
It is shown that fault equivalence and fault dominance relations defined based on the sets of completely specified test vectors that detect each fault may not hold when incompletely specified test vectors are used together with three-value simulation. Experimental results are presented to demonstrate the extent of this phenomenon. Its effects are discussed in general and in the context of a specific application. Possible solutions are also discussed.