An Overflow-Free Residue Multiplier
Taylor · IEEE Transactions on Computers · 1983
Residue arithmetic is receiving increased attention due to its ability to support very high-speed parallel arithmetic. However, dynamic range overflow remains a serious problem. Contemporary overflow management schemes rely on inefficient scaling algorithms. In this paper, an overflow-inhibiting residue multiplier is architected and tested. The system makes use the popularthree moduliset{2n − 1,2n, 2"+ 1}. Based on 4K high-speed memory technology, a practical 16-bit multiplier can be configured. An error model for the derived residue arithmetic unit is presented and experimentally verified.