A High-Speed 64b/66b Decoder Used in SerDes
Bin Wang, Qing Sheng Hu · Applied Mechanics and Materials · 2014
A high-speed 64b/66b decoder for SerDes system was designed in TSMC 0.18-μm CMOS Technology. The chip is composed of Block Sync, Descrambler, Decode Process and Receive Control. To make the system can be work in high speed, we use a lot of technology such as pipeline strategy, optimization of complicated logics and parallel descrambler.