HNCP-II: A 16-core 65nm microprocessor ASIC for image processing algorithms
Mohamed Amine Boussadi, Thierry Tixier, Alexis Landrault, Jean-Pierre Dérutin · 2014
In many video and image processing applications, complexity has reached a point where the performance requirements can no longer be supported by standard architectures based on a single processor. This is why many systems are based on multiprocessor architecture. In this paper, we present HNCP-II a 16-core flexible distributed memory ASIC dedicated to embedded application field (image processing applications). Connected through a torus on-chip network, each tile of the overall system includes an open-source RISC processor, a floating point unit, a video management module and a set of built in hardware features for multicore communication. This specific hardware enables to meet most relevant overall parallelism scheme (parallel skeletons) thanks to software-configurable modules. Results are presented for two image processing algorithms in term of execution time, speedup and efficiency. Area, power and timing performance of the synthesized ASIC are given for a CMOS 65nm technology node.