Timing-Aware Multiple-Delay-Fault Diagnosis
Vishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Hans Tsai, Janusz Rajski · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2009
With feature sizes steadily shrinking, manufacturing defects and parameter variations often cause design timing failures. It is essential that those errors be correctly and quickly diagnosed. In this paper, we analyze the multiple-delay-fault diagnosis problem and propose a novel approach to solve it. We enhance the diagnostic resolution by processing failure logs at various slower-than-nominal clock frequencies. We evaluate the utility ofn-detection and timing-aware automatic-test-pattern-generated (ATPG) sets. Experimental results show that using timing-aware ATPG sets yields better diagnostic resolution and results in better delay-defect-size estimations compared ton-detection ATPG sets. We experimentally determined our diagnosis algorithm's sensitivity to delay variations.