Multi-log/sub 2/N networks and their applications in high-speed electronic and photonic switching systems
Chin‐Tau Lea · IEEE Transactions on Communications · 1990
A class of switching networks is proposed to remove the time and space bottlenecks of conventional RAM-controlled switching architectures. The advantages of these networks, such as tolerance of faults O(log/sub 2/N) stages between each inlet-outlet pair, self-routing capability, easy path hunt, and easy fault diagnosis, and their implementation are discussed. Graph theory is used to construct strictly nonblocking or rearrangeable nonblocking networks that are based on the new architecture.>