A method of reducing aliasing in a built-in self-test environment
K. Akiyama, Kewal K. Saluja · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1991
A method of reducing aliasing in built-in self-test of VLSI circuits is proposed. The method is based on the use of transition count testing. A new formulation of the problem is given in terms of finding a test generator as opposed to solving the problem at the data compaction end. An algorithm is proposed which can be used to find a counter-based test pattern generator. This test generator tests a circuit exhaustively or pseudo-exhaustively so that the aliasing is reduced substantially provided the data compactor used is a transition counter. Experimental results are presented to substantiate these claims.>