Arithmetic unit based on a high-speed multiplier with a redundant-binary addition tree
Naofumi Takagi · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 1991
An arithmetic unit based on a high-speed multiplier with a redundant binary addition tree is proposed. It is efficient for numerical computations with iteration of multiplications and addition/subtractions. A new multiplier recoding method makes the arithmetic unit efficient for these computations.