JTAG-based bitstream compression for FPGA configuration
Rui Jia, Fei Wang, Rui Chen, Xingang Wang, Haigang Yang · 2012
A novel circuit architecture for configuration bitstream compression based on JTAG is proposed. The circuit decompresses and compresses bitstream while FPGA is configured and performs readback accordingly. The compression and decompression operations are implemented dynamically by a concise hardware architecture within the framework of IEEE standard 1149.1. Run Length Encode/Decode (RLE/D) algorithm is used for compression coding. Using Chartered 0.13um single-poly-8-metal process, the chip size is 0.01 mm2.