Implementation of improved error trapping decoder for multiple error correcting cyclic codes in a soft core processor
Sutanu Gayen, B. Dam, D Chandra Patranabis · Journal of Scientific & Industrial Research · 2008
This paper presents implementation of Tadao Kasami decoding algorithm for improved error trapping decoding and firmware realization details. Algorithm has been applied to cyclic (n, k) codes [Golay (23, 12) and BCH (31, 16)] for triple error correction. Microblaze 32-bit soft core processor was used with a Xilinx Spartan3 FPGA. To test decoder functionality, a test procedure with all possible error combination is devised. Profiling of execution time with no error and with error is presented along with hardware resource utilization of FPGA.