A DSP ASIC design flow based on VHDL and ASIC-emulation
Jan Andersson · European Design Automation Conference · 1995
In an ASIC project VHDL-simulation, VHDL-synthesis and ASIC-emulation has been used. The project is completed and described in this paper. As an introduction a short presentation of the end product, MINI-LINK, is given. The project started with a rough design flow. The characteristics of the ASIC and its target formed the details as time went by. The ASIC, its target and the final design flow is presented. One step in the design flow is verification by ASIC-emulation. What ASIC-emulation is, why it was chosen and how it was used in the project will be discribed. The paper is concluded with a summary of the results.