FPGA implementation of multiplierless 5/3 LeGall discrete wavelet transform using lifting approach
Naregalkar Akshay, Basavoju Harish, Sujata Dhanorkar, B. L. Raju · 2011
For the hardware implementation architecture for discrete wavelet transform (DWT), one current focus is how to efficiently decrease hardware complexity and reduce hardware overhead while the need of real-time system is met. The conventional DWT makes use of convolution, so it needs a lot of computation and hardware resources. This case is hard to imagine for the hardware architecture which has high requirement of real time and small hardware overhead.