A Cordic-Based Reconfigrable Systolic Array Processor for MIMO-OFDM Wireless Communications
Katsutoshi Seki, Tomoyoshi Kobori, James Okello, Masao Ikekawa · SiPS ... design and implementation - IEEE Workshop on Signal Processing Systems · 2007
A reconfigurable systolic array processor based on a coordinate rotation digital computer (CORDIC) algorithm is proposed for MIMO-OFDM baseband processing. With CORDIC, the processor provides high computation efficiency, and a multi-thread interleaving architecture offers the advantage of a simple data transfer mechanism. Also presented are an array mapping method for calculating MMSE filter coefficients and a comparison of the processor's performance with that of dedicated hardware. Despite its flexibility, the processor achieves a computational density of 57% that of dedicated hardware.