HiveFlex Video VSP1 Demonstration
Aleksandar Beric, C.A. Alba Pinto · 2006
This work presents a real-time demonstrator system for the VSP1 Tile. The complete 8-way SIMD VSP1 Tile is implemented on the demonstration platform based on the Xilinx Virtex2 XC2V8000 FPGA chip. The application running on a VSP1 Tile is spatial up-scaling. This is a challenging application since it is based on a pixel-based algorithm using content adaptive filtering. The FPGA running on 25 MHz is capable of achieving 17.3 fps for input sequence (320*192) producing four times bigger output sequence (640*384)