An Error Correcting Method of BCH Code Applicable to Memory
Yi Yun Zhang, Hou Peng Chen, Zhi Tang Song, Ge Zi Li · Applied Mechanics and Materials · 2014
An error correcting method of BCH code applicable to memory is proposed. The reliability and yield of memories can be efficiently improved by error correcting codes. Due to the limited length of data transfer bits in certain interfaces, check bits are not fully used by most BCH codes. The proposed method takes advantage of the nature of BCH codes to make full use of the check bits, so that more errors can be corrected than the original method. The algorithm can be achieved by pure logic circuits in a parallel way with only gate delay, suitable for special timing applications. The improvement of certain BCH code is evaluated by C++ and the hardware implementation is presented by FPGA.