A 45nm SOI embedded DRAM macro for POWER7TM 32MB on-chip L3 cache
John Barth, Don Plass, Erik Nelson, Charlie Hwang, Gregory Fredeman, Michael A. Sperling, Abraham Mathews, William R. Reohr, Kavita Nair, Nianzheng Cao · 2010
This paper presents a 1.7 ns-random-cycle SOI embedded-DRAM macro developed for the POWER7¿ high-performance microprocessor and introduces enhancements to the micro-sense-amplifier (¿SA) architecture. The macro enables a 32 MB on-chip L3 cache, eliminating delay, area and power from the off-chip interface.