A pipelined multiplication unit
He Jing, Han Yue-qiu · 2003
A multiplication unit is described in this paper. The unit can perform 16-bit, 32-bit, single precision and double precision multiplication. BOOTH 2 encoding is used, and 54-bit multiplier is partitioned into multiple sub-multipliers that can operate either as an independent multiplier or as a part of a larger one, so that average latency is reduced and the hardware cost is reduced. Inside each small multiplier, BOOTH 2 encoding is optimized and 4:2 compressors are used to improve the performance. The design is synthesized, implemented and verified with FPGA, and can operate at 25 MHz. The unit is used in the design of a DSP processor.