Optimal-time multipliers and C-testability
Bernd Becker, Joachim Hartmann · 1990
After a brief review on testability aspects of parallel arithmetical units we focus on n-bit multipliers and especially consider a class of Wallace tree multipliers made suitable for VLSI design by Vuillemin and Luk [VULU].It is shown that for these circuits both optimal running time and optimal test complexity can be obtained.A complete test set according to the single cellular fault model is presented.(In this case, the single cellular fault model is superior to the classical single stuck-at model.)The proposed test only consists of 17 pattern8 for all n.Hence, the multiplier is C-testable, i.e. it can be tested by a number of input combination8 which is independent of the number of cells in the circuit.The extra test hardware is very small.Only two additional ports and n -2 internal connections are necessary.