Improving application performance with hardware data structures
Ravikesh Chandra, Oliver Sinnen · 2010
Contemporary processors are becoming wider and more parallel. Thus developers must work hard to extract performance gains. An alternative computing paradigm is to use FPGA technology in a reconfigurable computing environment-where both software and hardware can be specified. This has the potential to realise substantial performance gains in a variety of applications, however it is a daunting task as hardware development is required to harness the benefits. In this research the acceleration of common data structures-with the priority queue (PQ) as a case study-has been explored in the context of such a reconfigurable computing environment. A Java-based hybrid hardware/software PQ has been developed that is a 'drop-in' replacement for a software implementation; achieved by strictly adhering to the same programming interface. The accelerated PQ has demonstrated up to 3x speedup when performing a minimum spanning tree graph computation. Taking this further, a suite of accelerated data structures represents an attractive way for developers to harness the potential of reconfigurable computing in the future across a wide gamut of application domains.