A novel ASIC implementation of RSA algorithm
Zhu Keija, Xu Ke, Yang Wang, Min Hao · 2003
In this paper, a novel ASIC implementation of RSA algorithm is presented. By utilizing Yang's modified Montgomery algorithm, the over-large residue problem is eliminated. The multiplication and Montgomery modular reduction in modular multiplication are handled identically to minimize hardware cost. Microprogrammed control makes the architecture very flexible to support variable key lengths. These features make the chip very suitable for smart card applications. A RSA coprocessor based on the new architecture has been fabricated with 0.5 mm CMOS cell library. The coprocessor has 14 K gate counts and 3 mm2 die size with a maximum clock frequency of 40 MHz, which takes about 325 ms to encrypt/decrypt 1024-bit data.