Field-programmable gate array implementation of a systolic architecture for a morphology engine
Abdelaziz Chihoub, M. LaValva, J.Y. Avins, Jeff Turlip · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 1993
While morphology use is gaining in popularity, it can be a computationally intensive process. This is particularly true for applications requiring large structuring elements. In this paper we will describe the use of field programmable gate arrays (Xilinx 4000 FPGA family) to implement a systolic architecture for a morphology engine. The engine has a 14 bit data-path, a reconfigurable structuring element size and a 512 X 512 image size. We will describe the architecture, the FPGA implementation of the engine and the interface with the host (datacube).