Highly automated and efficient simulation environment with UVM
Hung-Yi Yang · 2014
As design becomes more and more complicated, functional verification is getting challenging than ever. The challenges come in twofold: verification is taking longer to finish and difficult to catch all functional errors. Surveys[1] shown that functional error has been the number one reason for re-spin. How well verification is done becomes a very important issue. Re-spin not only can cost a lot due to advancing of manufacturing process but also delays the time to market which could be even more costly than re-spin itself. In order to tackle these two challenges, industry has come up with a solution called Universal Verification Methodology (UVM)[2] in recent years. But even with UVM which standardized the way for designing testbench, a simulation environment has to be well designed to take advantage of UVM and provide management of running large amount of simulations/regression in an efficient way.