19.2 A 93.4mm2 64Gb MLC NAND-flash memory with 16nm CMOS technology
Sungdae Choi, Duckju Kim, Sungwook Choi, Byungryul Kim, Sunghyun Jung, Kichang Chun, Namkyeong Kim, Wanseob Lee, Taisik Shin, Hyunjong Jin, Cho Hyun-Chul, Sunghoon Ahn, Yonghwan Hong, Ingon Yang, Byoungyoung Kim, Pil‐Seon Yoo, Youngdon Jung, Jinwoo Lee, Jaehyeon Shin, Taeyun Kim · 2014
This paper presents a 64Gb MLC NAND-Flash memory fabricated with 16nm CMOS process technology to achieve high density and as small as 93.4mm2 die area. The chip consists of two planes of 1072 blocks each. A block consists of a string with 128 cells and a page size with 16KB and spare area for error-correction coding (ECC), totaling 4MB of capacity. The chip supports negative-level wordline drivability to increase cell Vth margin.