Debug architecture for the En-II system chip
Bart Vermeulen, Sjaak Bakker · IET Computers & Digital Techniques · 2007
A comprehensive system debug methodology is presented, which combines the state-of-the-art support for software, functional hardware and process technology debug. The application of this methodology to the 65-nm CMOS En-II SoC is described, containing among others a high-performance ARM CPU and a TriMedia VLIW DSP. The debug requirements and implementation choices made are explained in detail.