REPLICA T7-16-128 — A 2048-threaded 16-core 7-FU chained VLIW chip multiprocessor
Martti J. Forsell, Jussi Roivainen · 2014 48th Asilomar Conference on Signals, Systems and Computers · 2014
Processor-based solutions are getting increasingly popular over dedicated logic/accelerators among embedded system designers due to their flexibility and programmability. The drawbacks - weaker performance and higher power consumption - are usually compensated with multicore and application-specific technologies. Unfortunately, these optimizations - exploiting parallelism and heterogeneity - lead to direction that makes programming difficult and result to less flexible designs. REPLICA is VTT's effort to solve the performance and programmability problems of current multicore processors without tampering flexibility. For performance, it addresses the essence of parallel computing - cost-efficient synchronization, high intercommunication bandwidth and latency toleration - with a new collection of architectural techniques: multithreading, sparse/multimesh network-on-chip and wave-based synchronization. Programmability is made simple by supporting efficient execution of synchronous parallel algorithms and flexibility is provided with parametric nature of the architecture allowing for highly different configurations. In this paper we introduce a 2048-threaded 16-core prototype of the REPLICA chip multiprocessor. The main principles of the architecture as well as the structure of the prototype are explained. Preliminary comparison to current alternatives is given.