Delay-fault diagnosis by critical-path tracing
Patrick Girard, C. Landrault, S. Pravossoudovitch · IEEE Design & Test of Computers · 1992
A delay fault diagnosis process consisting of simulation of the fault-free circuit with a four-valued logic algebra and critical-path tracing from primary outputs to primary inputs is presented. An alternative to fault simulation, the method requires no delay-size-based fault models and considers only the fault-free circuit. A sensitivity analysis process for improving diagnosis accuracy is also presented.>