FIR filter implementation using bit-serial arithmetic and partial summation trees
S. G. Gibb, P. J. W. Graumann, Laurence E. Turner · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 1996
An architecture which efficiently implements a fixed coefficient FIR filter using pipelined bit-serial arithmetic is described. A specialized multiplier decomposition exploiting multiplier coefficient similarities is used to obtain a reduced hardware area implementation. A design methodology which supports the conversion of a frequency response specification into a gate level implementation of the filter is presented. An 89 tap FIR filter meeting a multi-band frequency response specification, with 16 bit internal data precision and a sample rate of 1.6 GHz for parallel input and output data is implemented on a single XILINX 4005PG156 FPGA device.