Optimization Methodology of Layer Numbers with Circuit/Process Co-Design
Takanori Kyogoku, Junpei Inoue, Hidenari Nakashima, Takumi Uezono, Kenichi Okada, Kazuya Masu · Japanese Journal of Applied Physics · 2006
The number of layers directly affects manufacturing cost, and it also has a trade-off with the circuit area in multilevel interconnection LSI. In this paper, we propose a co-design methodology for circuits and processes to optimize the number of interconnect layers. In the proposed methodology, the number of interconnect layers can be optimized in consideration of circuit area. Wire length distribution (WLD) is used to derive the optimized number of layers from a circuit netlist. Operating frequency and power consumption are estimated as functions of circuit area in the 180 nm process-technology node. From the analyzed results, it has been shown that circuit area has an optimum value to improve both operating frequency and power consumption.