Security-Aware Design Flow for 2.5D IC Technology
Yang Xie, Chongxi Bao, Ankur Srivastava · 2015
The increasing trend of outsourced fabrication in integrated circuit (IC) supply chain makes IC designs vulnerable to Intellectual Property (IP) piracy by untrusted foundries. 2.5D IC technology has shown the capability to counter this threat. By limiting the interposer layer of a 2.5D IC that contains inter-chip connections to be fabricated in a trusted foundry, the complete exposure of original design to an untrusted foundry is prevented. In this paper, we propose a security-aware physical design flow for 2.5D IC technology to prevent IP piracy based on IC testing rules and metrics. The partitioning phase utilizes the concepts of controllability and observability to conceal the functionality of a design and the placement phase generates obfuscated chip layouts that can withstand layout-geometry based attacks such as proximity attack. Simulation results show that our design flow is effective for producing secure chip layouts for outsourcing whose original netlist and functionality cannot be reverse-engineered based on layout-geometry information.