The Hardware Realization of the Bicubic Interpolation Enlargement Algorithm Based on FPGA
Yunshan Zhang, Yuhui Li, Jie Zhen, Jionghao Li, Ran Xie · 2010
There is an improvement to the Bicubic interpolation enlargement algorithm based on the hardware parallel processing in this article. Search table method used in this paper has avoided massive cubic and the floating numbers multiply operation. It reduces the computation load greatly. Convolution operation in tow directions, level and vertical, of the 4x4 picture element matrix on FPGA has been realized by LPM. The Bicubic interpolation enlargement algorithm is completely based on the hardware parallel characteristic to realize. This method has the superiority in the computation speed and occupies on the resources.