A physical unclonable function chip exploiting load transistors' variation in SRAM bitcells
S. Okumura, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto · 2013
We propose a chip identification (ID) generating scheme with random variation of transistor characteristics in SRAM bitcells. In the proposed scheme, a unique fingerprint is generated by grounding both bitlines. It has high speed, and it can be implemented in a very small area overhead. We fabricated test chips in a 65-nm process and obtained 12,288 sets of unique 128-bit fingerprints, which are evaluated in this paper. The failure rate of the IDs is found to be 2.1 × 10-12.