FPGA in Rough-Granular Computing: Reduct Generation
Maciej Kopczyński, Tomasz Grześ, Jarosław Stepaniuk · 2014 IEEE/WIC/ACM International Joint Conferences on Web Intelligence (WI) and Intelligent Agent Technologies (IAT) · 2014
In this paper we propose a combination of capabilities of the FPGA based device for computing reduct. Presented architecture has been tested on a real-world data. Obtained results confirm the huge acceleration of the computation time using hardware supporting reduct computation in comparison to software implementation.