Automatic Construction of On-line Checking Circuits Based on Finite Automata
Lucie Matuova, Jan Katil, Zdeněk Kotásek · 2014
In this paper, the approach to the automatic development of checking circuits for unit implemented in FPGA is described. The checking circuit, also denoted as online checker, introduces fault tolerance aspects to the unit. It provides the information about correctness of the unit output. Checkers are constructed from models inferred by active automata learning which is based on communication with a simulator. To implement the learning environment, LearnLib library has been employed. A platform for automatic construction of online checkers has been designed and implemented. The experimental part of the paper proves that it is possible to automatically generate the model for the online checker which describes the basic behaviour of the checked component. The obtained checker is up to six times smaller than the original component.