Hybrid architecture for analogue neural network and its circuit implementation
L. Chen, Martine Wedlake, G. Deliyannides, H.L. Kwok · IEE Proceedings - Circuits Devices and Systems · 1996
The paper describes a prototype GaAs Hopfield neural network IC designed with a hybrid architecture. This architecture uses both parallel summation and multiplication, and the neuron states are updated serially. For an N × N network, only N multipliers (with an adder) and one activation (function) circuit are required. In the implementation, we have developed a 16 neuron network chip using CCDs to form the weight storage array. The main part of the chip (except for the CCDs) was fabricated using a 0.8 µm depletion mode self-aligned gate process and the chip was tested successfully when configured to operate as an associative memory.