Split tiling for GPUs
Tobias Grosser, Albert Cohen, Paul H. J. Kelly, Jagannathan Ramanujam, Ponnuswamy Sadayappan, Sven Verdoolaege · 2013
Tiling is a key technique to enhance data reuse. For computations structured as one sequential outer "time" loop enclosing a set of parallel inner loops, tiling only the parallel inner loops may not enable enough data reuse in the cache. Tiling the inner loops along with the outer time loop enhances data locality but may require other transformations like loop skewing that inhibit inter-tile parallelism.