Configurations for I/sub DDQ/-testable PLAs
Manoj Sachdev, Hans G. Kerkhoff · IEEE Design & Test of Computers · 1999
In these two PLA configurations, adjacent precharge lines activate, and adjacent evaluation lines evaluate, to complementary logic levels. This design-for-test technique makes it possible to use I/sub DDQ/ tests to defect all likely bridging faults-for the most part independently of the PLA's implemented function.