An estimation and exploration methodology from system-level specifications
Sébastien Bilavarn, Guy Gogniat, Jean Luc Philippe · 2003
Rapid evaluation and design space exploration from early specifications are important issues in the design cycle. We propose an original area vs. delay estimation methodology that targets reconfigurable architectures. Two main steps compose the estimation flow: i) structural estimations where architectural solutions are defined at the RT level, this step is technological independent and performs an automatic design space exploration and ii) physical estimations which perform technology mapping to the target reconfigurable architecture. Experiments conducted on Xilinx (XC4000, Virtex) and Altera (Flex10K, Apex) components for a 2D DWT and a speech coder lead to an average error of about 10% for temporal values and 18% for area estimations. The originality of this work is mainly a complete and realistic cost characterization that takes care of the processing, memory and control units, and supplies architectural information for the design of each solution.