Generating formal hardware verification properties from Natural Language documentation
Christopher B. Harris, Ian G. Harris · 2015
In the modern Application Specific Integrated Circuit (ASIC) design cycle, correctness properties for functional verification are usually created by an engineer whose task is to read the system documentation and manually generate a set of formal statements in the chosen verification language. This process is typical of the reason why up to 60% of engineering effort is spent on verification and test activities. We present a formal attribute grammar as the basis for a Natural Language based translation system which automatically generates syntactically correct verification properties in Computation Tree Logic (CTL) from Hardware Description Language (HDL) code comments written in English. The system is evaluated using verification information from an implementation of the PCI bus specification included in the Texas-97 Verification Benchmark suite and successfully translates English to valid CTL in 91% of test cases. The automatically generated CTL properties are compared to CTL properties included in the benchmark and model checking is used to determine the equivalency of generated and benchmark properties. While most generated properties are equivalent, some were found to include additional terms which result in CTL which more closely reflects designer intent.